Sujanth Roy J, G Lakshminarayanan. Low Power, Area Efficient Architecture for Successive Cancellation Decoder. EMITTER Int’l J. of Engin. Technol. [Internet]. 2022Jun.20 [cited 2024Nov.22];10(1):170-82. Available from: https://emitter2.pens.ac.id/ojs/index.php/emitter/article/view/650